01352nas a2200145   4500008004100000245012000041210006900161300001500230520073200245100002100977700001900998700002701017700001901044856014301063       1998                        eng d00aAnalytical Performance Models for Multistage Interconnection Networks with finite, infinite and zero length buffers0 aAnalytical Performance Models for Multistage Interconnection Net  a 169 - 1823 aMultistage Interconnection Networks (MINs) with crossbar switches have been used
to interconnect processors and memory modules in parallel multiprocessor systems.
They also play an increasingly important role in the development of ATM networks.
In this paper we analyze the general case of MINs, made of kxk switches with
finite, infinite or zero length buffers (unbuffered). The exact solution of the steady
state distribution of the first stage is derived for all cases. We use this to get an
approximation for the steady state distributions in the second stage and beyond. In
the case of unbuffered switches we reach the known exact solution for all the stages
of the MIN. Our results are validated by extensive simulations.1 aBouras, Christos1 aSpirakis, Paul1 aTriantafillou, Vasilis1 aGarofalakis, J  uhttp://telematics.upatras.gr/telematics/publications/analytical-performance-models-multistage-interconnection-networks-finite-infinite-and